The effects of process variations on the performance of MCM-D interconnects

Author

Solomon, Dawit ; Adams, Robert ; Lanka, Mike ; Berry, Ken ; El-Kilani, Saddah

Author_Institution

Polycon Corp., Tempe, AZ, USA

fYear

1993

fDate

4-6 Oct 1993

Firstpage

298

Lastpage

302

Abstract

The performance of thin film interconnects is dependent upon successful interaction between design and the fabrication process. The functional verification of process tolerances to achieve the originally simulated design requirements is addressed. Variational analysis results about the nominal design value are presented and compared with initial simulation results. Interconnect capacitance and impedance variations as a function of conductor and dielectric geometry are shown. The analysis shows that the process is capable of giving an impedance within 10% of the nominal design value

Keywords

S-parameters; capacitance; equivalent circuits; impedance matching; integrated circuit interconnections; integrated circuit packaging; multichip modules; tolerance analysis; MCM-D interconnects; S-parameter; capacitance variations; conductor geometry; dielectric geometry; effects of process variations; equivalent circuit; functional verification; impedance variations; nominal design value; performance; process control charts; process tolerances; simulated design requirements; thin film interconnects; variational analysis; Chemical technology; Conductors; Dielectric substrates; Dielectric thin films; Fabrication; Impedance; Nonhomogeneous media; Stripline; Testing; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Manufacturing Technology Symposium, 1993, Fifteenth IEEE/CHMT International

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-1424-7

Type

conf

DOI

10.1109/IEMT.1993.398189

Filename

398189