Design of stable high order 1-bit sigma-delta modulators

A method for designing stable 1-b high-order (⩾3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizer´s gain in the modulator at the present clock period determines the modulator´s stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear analog/digital converter. Examples with third-, fourth-, fifth-, and sixth-order sigma-delta modulators are given to explore the use of the proposed method in practice. With the designed sixth-order modulator it is possible to achieve 23-b signal-to-quantization noise ratio at the oversampling ratio of 64