Title :
A partitioning advisor for studying the tradeoff between peripheral and area array bonding of components in multichip modules
Author :
Sandborn, Peter A. ; Abadir, Magdy ; Murphy, Cynthia F.
Author_Institution :
Microelectron. & Comput. Technol. Corp., Austin, TX, USA
Abstract :
The tradeoff between peripheral I/O format die (for wire bonding, tape automated bonding, or peripheral flip chip bonding) and area array I/O format die (for flip chip bonding) is examined as a function of partitioning a fixed functionality into a variable number of die. The comparison is made in the context of a multichip module (MCM). The automated analysis approach concurrently considers module size, thermal and electrical performance, and cost (including module level test and network) to assess the overall applicability of one bonding format over the other
Keywords :
circuit layout CAD; flip-chip devices; integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; integrated circuit yield; lead bonding; logic partitioning; multichip modules; tape automated bonding; SUSPENS model; area array bonding; automated analysis approach; cost; electrical performance; fixed functionality; module level test; module size; multichip modules; partitioning advisor; peripheral I/O format die; peripheral flip chip bonding; tape automated bonding; thermal performance; variable number of die; wire bonding; Cost function; Flip chip; Logic testing; Multichip modules; Packaging; Performance analysis; Performance evaluation; System testing; Wafer bonding; Wire;
Conference_Titel :
Electronic Manufacturing Technology Symposium, 1993, Fifteenth IEEE/CHMT International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-1424-7
DOI :
10.1109/IEMT.1993.398192
