An oversampled sigma-delta A/D converter circuit using two-stage fourth order modulator

A sigma-delta analog/digital (A/D) converter realization using a two-stage fourth-order modulator architecture and a fifth-order digital running-sum decimation filter is presented. The analog part of the converter consists of two cascaded second-order modulators. Scaling is used between the sections in order to achieve the modest requirements for component matching and the integrator´s gain and phase. A digital running-sum filter is used for the decimation to 4f_s or 2f_s. A dedicated seven-instruction filter processor is designed to perform the final decimation and I/O-communication. The whole system operates on a single 5-V operation voltage