A modified Rijndael algorithm and it´s implementation using FPGA

Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. A modified Rijndael algorithm capable of encrypting a 128 bit input/output/key is presented. The presented algorithm depends on substitution and permutation network (SP-Network) rather than feistel network. A new stage is proposed in the encryption process. The introduced architecture was implemented by VHDL, schematic and core generator - Based Design which are synthesized, placed and routed in Virtex XCV800-6bg432 which resulted in an optimized area (7148) slices and (44) MHz clock speed. Post simulations for major functions and the final algorithm are presented and discussed.