High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder

This paper presents a hardware proposal of an arithmetic encoder for the H.264/AVC CABAC entropy encoder. Three different architectures are presented capable of reaching high definition encoding levels with bin processing rates ranging from 0.63 to 1 bins per clock cycle. ASIC and FPGA synthesis results from the proposed architectures show that all of them are able to reach the required bitrate for the Level 5 (very high definition) of the H.264 video encoding standard. These results present a maximum efficiency of 167 kBins/Gate.s and 105 GBins/J.