DocumentCode
2666105
Title
Yield enhancement by tube redundancy in CNFET-based circuits
Author
Ashraf, Rehman ; Nain, Rajeev K. ; Chrzanowska-Jeske, Malgorzata ; Narendra, Siva G.
Author_Institution
Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
fYear
2010
fDate
12-15 Dec. 2010
Firstpage
442
Lastpage
445
Abstract
This paper analyzes the functional yield of CNFET based circuits when the metallic tubes are removed by extra processing steps. Functional yield for various gates is obtained through both Monte-Carlo (MC) simulations and analytical models. Tube Level Redundancy (TLR) is proposed to increase the functional yield of gates to an acceptable level when a large fraction of tubes are removed. Our results are very promising and indicate that when critical paths are considered, almost 100% yield can be achieved for relatively complex systems.
Keywords
Monte Carlo methods; carbon nanotubes; circuit simulation; field effect transistors; integrated circuit yield; redundancy; CNFET-based circuit; Monte Carlo simulation; TLR; carbon nanotube; metallic tube redundancy; tube level redundancy; yield enhancement; CMOS integrated circuits; CMOS technology; Electron tubes;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location
Athens
Print_ISBN
978-1-4244-8155-2
Type
conf
DOI
10.1109/ICECS.2010.5724544
Filename
5724544
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