VLSI implementation and performance of turbo decoding stopping criteria

An extension to the HDA termination criterion, the hardware implementation, and the performance of four stopping criteria for turbo decoders are presented in this paper. The proposed criterion is shown to substantially increase the error correction capabilities in terms of BER. A performance comparison in terms of BER of Turbo decoders with fixed number of iterations and early stopping via termination criteria is presented. It is shown that close to optimal error correcting performance is achieved with minimal hardware increase that can significantly improve decoding throughput.