Single-chip 1062 Mbaud CMOS transceiver for serial data communication

This work implements the media independent functions specified in the emerging ANSI fibre channel standard at 1062.5 Mbaud. Integrated onto a single CMOS chip are: two phase-locked loops (PLL) for clock generation and clock recovery, a selectable 1B or 2B parallel interface with corresponding multiplexer and demultiplexer for parallel-to-serial and serial-to-parallel conversion, word alignment logic for byte synchronization, 8B/l0B coder and decoder, and high-speed differential CMOS PECL drivers and receivers for the serial I/O. The chip measures 3.9/spl times/4.5 mm/sup 2/ with 100 I/O and dissipates 1.2 W at 1062 Mbaud with a 3.6 V supply. This design achieves higher-speed operation than previous CMOS work with similar integration, and lower power dissipation with higher integration than bipolar implementations at comparable speeds.