Memory-aware multiple reference frame motion estimation for the H.264/AVC standard

This paper presents an architecture for Multiple Reference Frame Motion Estimation (MRF-ME) targeting H.264/AVC standard. MRF introduces issues regarding processing throughput and memory access. In this context, this work proposes a memory-aware architecture for MRF-ME that relies on data reuse and current block parallelism. The data reuse scheme guarantees a reduction of almost 70% in the number of external memory accesses when compared with a traditional approach. The architecture was synthesized targeting a Xilinx FPGA device and it is capable of processing high definition (HD) videos in real time (30fps), with very good processing rates results when compared with related works. This solution is based on one single view, but it is being used as base to design an architecture which will be able to process multi view videos as defined in the H.264/AVC MVC extension.