3.5 Gb/s/spl times/4-Ch Si bipolar LSIs for optical interconnections

Author

Ishihara, N. ; Fujita, S. ; Togashi, M. ; Hino, S. ; Arai, Y. ; Tanaka, N. ; Kobayashi, Y. ; Akazawa, Y.

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

34

Lastpage

35

Abstract

The transmitter and receiver LSIs described here include a 5-to-1 multiplexer, 1-to-5 demultiplexer, optical interface and analog phase-locked loop (PLL) circuits that generate 3.5 GHz clock and retimed data. The chips make it possible to connect twenty pairs of 700 Mb/s electrical ports (14 Gb/s throughput) through four fibre channels without external elements even for the PLL.

Keywords

bipolar analogue integrated circuits; bipolar digital integrated circuits; demultiplexing equipment; elemental semiconductors; large scale integration; multiplexing equipment; optical interconnections; optical receivers; optical transmitters; phase locked loops; silicon; synchronisation; time division multiplexing; timing circuits; 14 Gbit/s; 3.5 GHz; 3.5 Gbit/s; 700 Mbit/s; Si; Si bipolar LSI devices; analog PLL circuits; analog phase-locked loop; demultiplexer; fibre channels; multiplexer; optical interconnections; optical interface; receiver LSI; transmitter LSI; Circuits; Clocks; Large scale integration; Optical amplifiers; Optical interconnections; Optical noise; Optical receivers; Phase locked loops; Pulse amplifiers; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535264

Filename

535264