1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Author

Kuroda, Tadahiro ; Fujita, Takashi ; Itabashi, Yosuke ; Kabumoto, S. ; Noda, Masaki ; Kanuma, A.

Author_Institution

Toshiba Corp., Kanagawa, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

36

Lastpage

37

Abstract

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 /spl mu/m, 15 GHz bipolar process operate with a -2 V single power supply, and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply.

Keywords

bipolar logic circuits; data communication equipment; demultiplexing equipment; digital communication; emitter-coupled logic; multiplexing equipment; time division multiplexing; 1.2 micron; 1.65 Gbit/s; 1.8 Gbit/s; 15 GHz; 2 V; 3-level series-gating ECL circuits; 60 mW; 80 mW; ECL circuit techniques; bipolar process; demultiplexer IC; low power dissipation; multiplexer IC; power-delay products; single power supply; three-level series gating; Bipolar transistors; Circuit testing; Delay; Logic circuits; Logic gates; Multiplexing; Power dissipation; Power supplies; Stacking; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535265

Filename

535265