Genetic algorithm based variable ordering of BDDs for multi-level logic optimization with area-power trade-offs

Boolean logics when implemented as BDDs can be graphically manipulated to reduce the number of nodes and hence the area. Ordering of BDD nodes play a significant role in this context. Most of the algorithms for input variable ordering for OBDD focus primarily on area minimization. However, suitable input variable ordering helps in minimizing the power consumption also. In this particular work, we have adopted a genetic algorithm based technique to find an optimal input variable order, while node reordering is taken care by the standard BDD package. Experimental results show a substantial saving in area and power. We have also compared our technique with other standard methods of variable ordering for OBDDs and found to produce superior results.