Synthesis of provably-correct hardware with options

This paper describes a formal high-level synthesis framework that is used to automatically generate provably-correct hardware from high-level, behavioural, algorithmic program code, with options of memory use and target FSM+datapath configurations. The correctness of the generated hardware accelerators is ensured by the use of compiler-generator and logic programming techniques. Internal, on-chip or external, shared memory use, as well as generation of massively-parallel or classic FSM+datapath can be selected via the use of compilation options. The required I/O and memory interfaces and communication handshake protocols are automatically generated by the hardware compiler. The generated hardware states are optimized with the use of the PARCS (resource-constrained) algorithm. The suitability of the presented design framework is proven with a number of test benchmarks including a MPEG video compression design.