A 900 Mb/s bidirectional signaling scheme

This bidirectional scheme is implemented on a 1.2 M transistor chip fabricated in 0.6 /spl mu/m CMOS. The chip has about 100 simultaneously switching outputs, including two 16 b wide bidirectional data ports. Synchronous clocking captures data at the inputs. A clock accompanies data, and is centered in the data cell using a delay-locked loop. A small FIFO in the receiver resynchronizes the data to the clock of the receiver. In a system, this chip using the bidirectional scheme operates up to 450 MHz, or 900 Mb/s per wire, over several inches of printed circuit board. This scheme operates over 30´ of coaxial cables at 390 MHz, and 8´ of flat ribbon cable at 300 MHz.