DocumentCode :
2667403
Title :
A low-area filter bank design methodology for on-chip ADC testing
Author :
Mechouk, Nicolas ; Dallet, Dominique ; Bossuet, Lilian ; Le Gal, Bertrand
Author_Institution :
IMS, Univ. of Bordeaux, Talence, France
fYear :
2010
fDate :
12-15 Dec. 2010
Firstpage :
718
Lastpage :
721
Abstract :
This paper focused on a filter bank study used for ADC BIST. Filter selection to separate spectral components of an analog-to-digital converted signal are discussed. Regarding the BIST context, a method to realize the lowest cost filter bank is proposed. This task has been done taking into account the wordlenght of the input and clock frequencies and the filter coefficient values.
Keywords :
analogue-digital conversion; built-in self test; channel bank filters; integrated circuit design; integrated circuit testing; ADC BIST; analog-to-digital converted signal; clock frequencies; filter selection; low-area filter bank design methodology; on-chip ADC testing; Europe; Signal to noise ratio; Simulation; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-4244-8155-2
Type :
conf
DOI :
10.1109/ICECS.2010.5724613
Filename :
5724613
Link To Document :
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