A continuous-flow, Variable-Length FFT SDF architecture

This paper presents a FFT architecture, which processes FFT frames of various size in a continuous-flow fashion. The organization is based on the Single-path Delay Feedback (SDF) scheme and it computes mixed radix FFT algorithms with radixes 2, 2², 2³ and 2⁴. The proposed SDF is able to execute FFT of size varying from 128 to 2048 in continuous-flow by exploiting the memory of each stage for efficiently storing the elements of any FFT frame-size. The design handles FFT size variation without requiring additional buffers and/or idle time for reconfiguration, while it keeps the complexity and the memory size comparable to that of the radix-2 SDF for 2048 points. A FPGA implementation verifies the results.