150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Two 0.9 /spl mu/m CMOS chips serve for burst-mode clock and data recovery applications specific to passive optical network (PON) systems. In each case, a core, first order clock recovery circuit is realized by two gated ring oscillators, indirectly frequency-tuned by a phase-locked loop using a third replica oscillator and a local reference signal. Instantaneous phase locking is guaranteed by restarting the gated oscillators every time input data transitions occur. This method has been demonstrated to be precise enough to handle input data patterns containing hundreds of bits between transitions without errors. In addition, the circuit is small and dissipates low power. However, the recovered clock signal thus obtained inherits all jitter present in the input data signal. This shortcoming has been overcome in the present designs by two different methods. The results are the total elimination of jitter propagation and the generation of clean data and clock output signals. The first chip operates at 150 Mb/s. Since the data is demultiplexed into 8 channels, the local reference signal runs eight times slower than the transmission rate. This allows ample time for jitter-rejection processing. The second chip operates at 30 Mb/s without a demultiplexer. The jitter rejection is accomplished with an elastic store based on five 1 b registers.