Column parallel single-slope ADC with time to digital converter for CMOS imager

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. Single-slope ADCs have been used as column parallel ADCs for CMOS image sensors. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2ⁿ. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability. We designed a 12-bit ADC, which consists of the 3-bit TDC and the 9-bit-single-slope ADC, by using a 0.25-μm CMOS process. Through SPICE simulation, we confirmed our single-slop ADC to be more consistent, have more robust meta-stability, and achieve higher-speed ADC operation at 200-MHz clock than the conventional single-slope ADC. The simulated DNL and INL were ±0.25 LSB and ±0.43 LSB.