A digital processor for full calibration of Pipelined ADCS

A digital full calibration processor is proposed to calibrate most known errors in Pipelined ADCs. This approach does not change internal parts of an ADC and compensates errors by digital post-processing of the output bits. The main idea behind the presented technique is to design a processor to find a correction function that gives the relation between the uncalibrated outputs and the calibrated ones. To verify the algorithm, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with nonideal factors in the SIMULINK with a 5.34 MHz sinusoidal input and a 100 MHz sampling frequency. The SNDR is improved from 45 dB to 69 dB and the SFDR is increases from 45.5 dB to 90 dB. The described algorithm has been implemented on a virtex-4 LX25 FPGA from Xilinx.