Mismatch aware power and area optimization of successive-approximation ADCs

Author

Mao, Jia ; Jonsson, Fredrik ; Zheng, Li-Rong

Author_Institution

iPack Center, R. Inst. of Technol. (KTH), Stockholm, Sweden

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

882

Lastpage

885

Abstract

In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it is able to minimize power dissipations by reducing the size of the unit capacitor area without dynamic range degradation due to capacitor mismatch. As a case study, a low power 12 bits SAR ADC has been designed in 0.18 μm CMOS process, with 1-100 kHz sample rate.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit noise; low-power electronics; power aware computing; CMOS process; area optimization; area-constrained ADC; device mismatch; device noise; low power ADC; mismatch aware power; power dissipations; process mismatch; quantization noise; size 0.18 mum; successive approximation register analog-digital converter; successive-approximation ADC; unit capacitor area size; word length 12 bit; Indexes; Registers; ADC; Capacitor mismatch; power optimization; successive approximation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724653

Filename

5724653