Dual band CMOS LNA design with current reuse topology

Author

Ben Amor, Meriam ; Fakhfakh, Ahmed ; Mnif, Hassene ; Loulou, Mourad

Author_Institution

Dept. of Electr. Eng., Nat. Eng. Sch. of Sfax, Tunis

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

57

Lastpage

61

Abstract

A new architecture of dual band receiver was introduced; it is able to make simultaneous operations at two different frequency bands. This architecture uses a new dual band low noise amplifier (LNA). A novel high gain and low noise amplifier topology is proposed. This paper presents a general methodology to design a LNA with current reuse topology for the two standards GSM and UMTS at 947.5MHz and 2.14GHz frequencies respectively, A fully integrated dual band LNA was designed using 0.35mum CMOS process. At 947.5MHz, the LNA exhibits a noise figure of 2.3dB, a voltage gain of 28dB, a CP1 of -12dBm. However, the LNA at 2.14GHz features a noise figure of 2.71dB, a voltage gain of 17dB and a CP1 of -4.5dBm. The power consumption is 37.5mW under a power supply voltage of 2.5V

Keywords

CMOS integrated circuits; low noise amplifiers; receivers; 0.35 micron; 17 dB; 2.14 GHz; 2.3 dB; 2.5 V; 2.71 dB; 28 dB; 37.5 mW; 947.5 MHz; CMOS process; current reuse topology; dual band receiver; low noise amplifier; 3G mobile communication; CMOS process; Design methodology; Dual band; Frequency; GSM; Low-noise amplifiers; Noise figure; Topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708675

Filename

1708675