DocumentCode :
2668928
Title :
Verification flow optimization using an automatic coverage driven testing policy
Author :
Lahbib, Younes ; Missaoui ; Hechkel, Maher ; Lahbib, Dhafer ; Mohamed-Yosri, Badreddine ; Tourki, Rached
Author_Institution :
ST Microelectron., Inc., Tunis
fYear :
2006
fDate :
5-7 Sept. 2006
Firstpage :
94
Lastpage :
99
Abstract :
SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
Keywords :
automatic testing; formal verification; integrated circuit testing; SCV; SystemC verification library; dynamic verification; functional verification; hardware simulation; property specification language; test bench automation; verification flow optimization; Automatic testing; Automation; Circuit simulation; Circuit testing; DH-HEMTs; Electronic equipment testing; Hardware; Microelectronics; Productivity; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on
Conference_Location :
Tunis
Print_ISBN :
0-7803-9726-6
Type :
conf
DOI :
10.1109/DTIS.2006.1708699
Filename :
1708699
Link To Document :
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