Design of 4-bit parallel sub-sampling A/D converter for IR-UWB receiver

This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband (IR-UWB) receiver with the sampling rate of 2.112 GS/s. The ADC´s specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This design is simulated in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR in 4.8 GHz bandwidth with 36 mW power consumption and the Figure of Merit (FOM) is 0.24 pJ/step.