Design, validation and FPGA implementation of a brushless DC motor speed controller

The brushless DC (BLDC) motors have become the common choice in low power, high speed, high accuracy applications and this imposed the need for efficient and low cost motor control drives. In this paper, a design method for a digital controller implemented in a low cost field programmable gate array (FPGA) is presented. The design is done by schematic capture and Simulink block diagram capture. The developed design is validated in a modular fashion by Simulink-HDL (hardware description language) co-simulation and experimental results are provided. The main contribution is the presented controller design method for FPGA implementation, with special emphasis on simulation validation and FPGA debugging tools usage for signals extraction and analysis.