Performances comparison between multilevel hierarchical and mesh FPGA interconnects

Author

Marrakchi, Zied ; Mrabet, Hayder ; Mehrez, Habib

Author_Institution

Dept. ASIM-LIP6, Univ. Paris 6

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

166

Lastpage

171

Abstract

In this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed

Keywords

field programmable gate arrays; integrated circuit interconnections; logic design; network topology; programmable circuits; Manhattan mesh architecture; butterfly-fat-tree topology; downward network; field programmable gate array; mesh FPGA interconnects; multilevel hierarchical FPGA; multilevel hierarchical interconnects; unidirectional programmable networks; Circuit topology; Field programmable gate arrays; Integrated circuit interconnections; Joining processes; Logic; Network topology; Performance evaluation; Routing; Switches; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708712

Filename

1708712