Low power digital design using modified GDI method

Author

Balasubramanian, Padmanabhan ; John, Jomy

Author_Institution

Sch. of Electr. Sci., Vellore Inst. of Technol.

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

190

Lastpage

193

Abstract

GDI (gate diffusion input) based technique for low power combinational logic circuit design has been elaborately discussed and the advantage of this design style over static CMOS (SC) implementation and pass-transistor logic (PTL), with regard to power consumption, delay and area complexity is also described in recent literature (Morgenshtein, 2002). In this paper, we propose a couple of new GDI based cell designs, which are found to be much more power efficient in comparison with existing GDI based cell functionality. The significance of these designs is substantiated by the simulation results obtained for a 0.35 muM TSMC CMOS technology, where an improvement in power efficiency of the order of 2-3times is reported in the pre-layout stage for some widely used important digital arithmetic circuits

Keywords

CMOS logic circuits; combinational circuits; digital arithmetic; logic design; low-power electronics; 0.35 micron; combinational logic circuit design; digital arithmetic circuits; gate diffusion input; low power digital design; modified GDI method; pass-transistor logic; static CMOS; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Circuit simulation; Combinational circuits; Coupling circuits; Delay; Digital arithmetic; Energy consumption; Logic design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708713

Filename

1708713