Simultaneous delay optimization and depth reduction in logic trees with minimum resources

In this paper, we propose a logic synthesis technique that achieves delay optimization along with simultaneous depth reduction, apart from minimizing resources for a logic tree structure. Although it is a technology-independent scheme, it is guaranteed to enable better results overall, even after the technology-mapping phase, as evident from the results obtained due to the inherent nature of the heuristic. The practical results derived by targeting a SPARTAN III FPGA logic family (XC3S50-4PQ144) show that there is an explicit delay optimization by about 9.11%, reduction in logic depth by 26.63% and decrease in resource utilization by around 38.59%, on an average, in comparison with existing methods in literature