EDP optimized synthesis scheme for Boolean read-once functions

Author

Balasubramanian, Padmanabhan ; Theja S

Author_Institution

Sch. of Electr. Sci., Vellore Inst. of Technol.

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

409

Lastpage

412

Abstract

This paper presents a synthesis framework for the important class of non-regenerative Boolean read-once functions (BROF). A two-pronged approach is adopted, where the satisfiability of the circuit functionality with minimum no. of active gates is first given priority. The gate level realizations are then translated into circuit level implementations viz., static CMOS LECTOR and stacked CMOS LECTOR styles, to evaluate the efficacy of our proposition on the basis of energy delay product (EDP) metric. Furthermore, the effect of transistor reordering on the delay of CMOS digital circuits is investigated. The SPICE based simulation results obtained for a modest 0.35mum TSMC process are promising, as it reports 41.5% savings in EDP, 10.5% reduction in power and 17.7% decrease in delay, over the best of conventional methods

Keywords

Boolean functions; CMOS logic circuits; computability; high level synthesis; logic design; logic gates; 0.35 micron; CMOS digital circuits; EDP optimized synthesis scheme; SPICE based simulation; active gates; circuit functionality; circuit level implementations; energy delay product metric; gate level realizations; nonregenerative Boolean read-once functions; satisfiability; stacked CMOS LECTOR; static CMOS LECTOR; transistor reordering; Boolean functions; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay effects; Digital circuits; Energy consumption; Logic circuits; Terminology;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708715

Filename

1708715