Synchronization with timing recovery loop in UHF RFID reader receivers

Author

Wei, Peng ; Li, Bo ; Yang, Yuqing ; Min, Hao ; Wang, Junyu

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

1148

Lastpage

1151

Abstract

This paper focuses on synchronization of radio frequency identification (RFID) reader receivers, which plays a significant role for stability and efficiency of RFID systems. Performance of RFID reader suffers from a back-link-frequency variation of tags at a maximum of 22% according to widely used RFID standards. A new synchronization scheme employing timing recovery loop in RFID Reader Receivers is presented to solve the problem with less hardware cost. Simulation results give an improved performance compared with conventional schemes. The design is implemented on Xilinx Spartan-3E FPGA and function is verified on our RFID test platform.

Keywords

UHF integrated circuits; field programmable gate arrays; integrated circuit testing; radiofrequency identification; receivers; synchronisation; RFID test platform; UHF RFID reader receivers; Xilinx Spartan-3E FPGA; back-link-frequency variation; synchronization; timing recovery loop; Radiofrequency identification; Registers; Signal to noise ratio; RFID; Timing recovery; digital receiver; synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724720

Filename

5724720