Experimental results obtained from a 1.6 GHz CMOS quadrature output phase locked loop with on-chip DC-DC converter

This paper presents the measured results and characterisation of a 1.2 V CMOS low phase noise quadrature output phase locked loop (PLL) with an on-chip regulated DC-DC converter. In particular, it exhibits a phase noise response of less than -115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 38%. The automatic amplitude control loop in the VCO gives the facility to trade-off phase noise response with power consumption. In addition, this paper discusses important features of the DC-DC converter needed for reducing spurs in such applications. The results show the negligible effect of the on-chip DC-DC converter on the spur tone level of the PLL, provided a proper regulator scheme is used to limit the output voltage ripple.