DocumentCode
2669649
Title
Efficiency optimization of integrated DC-DC buck converters
Author
Sizikov, Gregory ; Kolodny, Avinoam ; Fridman, Eby G. ; Zelikson, Michael
Author_Institution
Electr. Eng. Dept., Technion - Israel Inst. of Technol., Haifa, Israel
fYear
2010
fDate
12-15 Dec. 2010
Firstpage
1208
Lastpage
1211
Abstract
An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. Microprocessors or chipsets exhibit wide dynamic range of load current varying from 50mA up to 1.5 A per phase at full operation. Peak efficiency is shown to occur when the load current related losses and the inherent losses of the DC-DC converter are equal. Efficiency optimization methods are described for light and heavy load scenarios. The primary design objective is to maintain the load at the peak of the efficiency curve. A SPICE based circuit model of a DC-DC converter is applied to validate the proposed analytic methods.
Keywords
DC-DC power convertors; microprocessor chips; optimisation; SPICE based circuit model; chipsets; current 50 mA to 1.5 A; integrated DC-DC buck converters; microprocessors; optimization methods; Pulse width modulation; air core inductor; frequency dependent losses; on-chip DC-DC efficiency;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location
Athens
Print_ISBN
978-1-4244-8155-2
Type
conf
DOI
10.1109/ICECS.2010.5724735
Filename
5724735
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