Low-resource ECDSA implementation for passive RFID tags

With the introduction of security functionality RFID is an emerging technology that has high potential in numerous of applications. In this paper we investigate the hardware implementation of public-key cryptography for passive RFID tags. We generate digital signatures according to the ECDSA algorithm for authentication of RFID tags in open-loop scenarios. The implementation of ECDSA is based on the recommended F_p160 SECG elliptic curve SECP160r1. In order to meet the fierce constraints concerning power consumption and chip area our design has a 16-bit word size. The hardware module consists of a latch based 90 × 16-bit dual-port RAM, a datapath with a 16 × 16-bit multiply-accumulate unit and a dedicated finite-state machine. The design requires a chip area of 18 247 GEs and has a power consumption of 860 μW at 1MHz using a 0.35 μm CMOS technology. In total, an ECDSA signature requires 511 864 clock cycles.