DocumentCode :
266980
Title :
Implementation of a driver circuit in 65nm CMOS technology for body-coupled communication
Author :
Maruf, Md Hasan ; Korishe, Abdulah ; Roy, Sandip
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden
fYear :
2014
fDate :
10-12 April 2014
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a newly cascaded voltage mode tri-state driver circuit for body-coupled communication (BCC) designed in 65 nm CMOS technology. Each stage of the driver circuit has been resized to meet the requirement of the BCC. It has a driving capability of 6 mA from 1.2 V supply with 10 MHz operating frequency. Different analysis has been performed to get the optimum results for the proposed circuit. The analysis shows cycle to cycle jitter to be less than one and power supply rejection ratio (PSRR) 65 dB, indicating the good emission of supply noise. In addition, the driver circuit does not require a filter to emit the noise because the body acts like a low pass filter.
Keywords :
CMOS integrated circuits; biomedical communication; driver circuits; BCC; CMOS technology; PSRR; body-coupled communication; cascaded voltage mode tri-state driver circuit; current 6 mA; cycle to cycle jitter; frequency 10 MHz; low pass filter; power supply rejection ratio; size 65 nm; voltage 1.2 V; Communications technology; Conferences; Decision support systems; Electrical engineering; BCC; PSRR; corner analysis; driver circuit; noise analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Engineering and Information & Communication Technology (ICEEICT), 2014 International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4799-4820-8
Type :
conf
DOI :
10.1109/ICEEICT.2014.6919109
Filename :
6919109
Link To Document :
بازگشت