A priority-based parallel architecture for sensor fusion

Author

Nishida, Kenji ; Toda, Kenji ; Takahashi, Eiichi ; Yamaguchi, Yoshinori

Author_Institution

Electrotech. Lab., Ibaraki, Japan

fYear

1994

fDate

2-5 Oct 1994

Firstpage

105

Lastpage

112

Abstract

The architecture described in this paper supports a wide (32-bit) priority field across the entire system, including processor elements and the interconnection network. The processing element has a hardware task queue to help manage tasks for two execution pipelines (one for executing tasks, and the other for communication). Its fast interrupt handling facility directly supports the wide priority field. The processing elements are connected via a prioritized multistage network that also supports the same wide priority field. Connecting up to 64 processors, the system offers the high performance in real-time processing needed for sensor fusion processing

Keywords

interrupts; multiprocessor interconnection networks; parallel architectures; pipeline processing; sensor fusion; execution pipelines; fast interrupt handling facility; hardware task queue; interconnection network; prioritized multistage network; priority field; priority-based parallel architecture; processor elements; sensor fusion; Bandwidth; Control systems; Intelligent actuators; Intelligent robots; Intelligent sensors; Parallel architectures; Parallel processing; Real time systems; Sensor fusion; Sensor systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Multisensor Fusion and Integration for Intelligent Systems, 1994. IEEE International Conference on MFI '94.

Conference_Location

Las Vegas, NV

Print_ISBN

0-7803-2072-7

Type

conf

DOI

10.1109/MFI.1994.398467

Filename

398467