Title :
Low Power Design for a Multi-core Multi-thread Microprocessor
Author :
Wang Yong-Wen ; Zheng Qian-Bing ; Dou Qiang ; Zhang Min-Xuan
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
Power efficiency of microprocessor is essential to green computing. As most microprocessors become multi-core and multi-thread, it´s important to study low power design for them. The architecture of MCMT, a multi-core multi-thread microprocessor, is described briefly in this paper. Several low power design techniques, including fine-grained clock gating, instruction throttling and adaptive L2 cache are presented to reduce both the dynamic power and the leakage power. Experimental results show that the presented techniques can meet the power constraints.
Keywords :
integrated circuit design; microprocessor chips; multi-threading; adaptive L2 cache; fine-grained clock gating; green computing; instruction throttling; low power design; multicore multithread microprocessor; Capacitance; Clocks; Hardware; Instruction sets; Logic gates; Microprocessors; Radiation detectors; cache; clock gating; instruction throttling; low power; multi-core multi-thread;
Conference_Titel :
Green Computing and Communications (GreenCom), 2010 IEEE/ACM Int'l Conference on & Int'l Conference on Cyber, Physical and Social Computing (CPSCom)
Conference_Location :
Hangzhou
Print_ISBN :
978-1-4244-9779-9
Electronic_ISBN :
978-0-7695-4331-4
DOI :
10.1109/GreenCom-CPSCom.2010.66