Design of an DFE equalizer ASIC chip using the MMA algorithm

Author

Shin, Dae K. ; Hwang, Seung J. ; Sunwoo, Myung H.

Author_Institution

Sch. of Electron. Eng., Ajou Univ., Suwon, South Korea

fYear

2000

fDate

2000

Firstpage

200

Lastpage

209

Abstract

This paper proposes a DFE (decision feedback equalizer) equalizer ASIC chip using the multi-modulus algorithm (MMA). We believe that it is the first effort to combine the DFE structure and the MMA algorithm. The proposed equalizer has been designed for 64/256 QAM demodulations. The existing MMA equalizer uses two transversal filters while the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. We have used the 0.35 μm standard cell library. The fabricated equalizer ASIC chip operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The total number of the gates is about 160,000

Keywords

application specific integrated circuits; blind equalisers; channel bank filters; decision feedback equalisers; demodulation; interference suppression; intersymbol interference; logic CAD; quadrature amplitude modulation; 0.35 mum; 64 Mbit/s; 64/256 QAM demodulation; 8 MHz; CAD tool; DFE ASIC chip; DFE filter banks; DSL; EER performance; HDTV; ISI; LMDS; MMA algorithm; bandlimited channels; blind equalizer; cable modem; channel adaptive performance; decision feedback equalizer; intersymbol interference; logic synthesis; multi-modulus algorithm; standard cell library; transversal filters; Algorithm design and analysis; Application specific integrated circuits; DSL; Decision feedback equalizers; Delay; Demodulation; HDTV; Least squares approximation; Logic; Power cables;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886717

Filename

886717