Design of a QPSK/16 QAM LMDS downstream receiver ASIC chip

This paper presents a QPSK/16 QAM LMDS (local multipoint distribution services) downstream receiver ASIC chip. The proposed LMDS chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE (decision feedback equalizer) structure using CMA (constant modulus algorithm). The symbol timing recovery uses the modified parabolic interpolator and the decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers