Non-Instruction Fetch-Based Architecture Reduces Almost 100 Percent of the Dynamic Power and Energy

This paper demonstrates the benefit of FPGAs for better power and energy efficiency when exploited for non-instruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100 percent of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems and to solve the dissipated power dilemma, as the heat becomes the bottleneck of traditional high frequency processors. If the same strategy is applied to mainstream computers and data center servers, we will not only reduce electricity bills but we will also contribute to greener computing by improving the IT sector´s CO2 emissions. The work involves three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs employ a single-purpose processor with different number of storage registers 2n and 2n² and the third design uses a computer system piloted by NIOS II/e processor with on-chip memory. The designs were captured in VHDL language and prototyped on an Alter a Cyclone II EP2C35F672C6 device. Both synthesis and place&route steps were performed with Quart us II 6.0 Web Edition. The experiments were made on Altera DE2 board. In this paper we have also clarified further the power estimation error of Alter a power estimation tools, which we have evaluated in.