Turbo codes on the fixed point DSP TMS320C55x

Author

Ngo, Tri ; Verbauwhede, Ingrid

Author_Institution

Philips Semicond., Irvine, CA, USA

fYear

2000

fDate

2000

Firstpage

255

Lastpage

264

Abstract

Turbo codes are introduced in 3rd generation wireless cellular standards for their superior coding gain. The MIPS requirements of turbo codes are however extremely high. This paper describes the implementation of a turbo-decoding algorithm on the TMS320C55x processor. The coding performance is evaluated with fixed-point arithmetic. A method to optimize the memory is also introduced to address the large data storage problem. The effect of finite word lengths is carefully examined to reduce the state metric normalization time and to achieve at the same time an acceptable bit error rate (BER). The coding gain of 5.8 dB for a BER of 10^-3 in 6 iterations is achieved with a frame size of 1 K bits and 50 Hz frame rate. Total MIPS estimate when using the max Log-MAP algorithm is 46 MIPS

Keywords

cellular radio; decoding; digital signal processing chips; fixed point arithmetic; telecommunication standards; turbo codes; 3rd generation wireless cellular standards; 46 MIPS; 50 Hz; BER; MIPS requirements; bit error rate; coding gain; coding performance; finite word lengths; fixed point DSP TMS320C55x processor; fixed-point arithmetic; frame rate; frame size; large data storage problem; max Log-MAP algorithm; memory optimisation; state metric normalization time; turbo codes; turbo-decoding algorithm; Bit error rate; Block codes; Code standards; Digital signal processing; Fixed-point arithmetic; Iterative decoding; Multiaccess communication; Optimization methods; Throughput; Turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886724

Filename

886724