Efficient mapping of CORDIC algorithms on FPGA

Author

Valls, Javier ; Kuhlmann, Martin ; Parhi, Keshab K.

Author_Institution

Dipt. Ingenieria Electron., Univ. Politecnica de Valencia, Spain

fYear

2000

fDate

2000

Firstpage

336

Lastpage

345

Abstract

This paper presents a study of the efficient mapping on FPGA of the operators required to implement redundant arithmetic based CORDIC algorithms. It is shown that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional ones. On the other hand, the speed advantages of the full-custom design has been lost, due to the longer routing delays caused by the increase of the fanout and the number of nets in the implementation of the redundant operators. Therefore, it is concluded that redundant arithmetic-based CORDIC methods are not suitable for implementation on FPGA

Keywords

field programmable gate arrays; mathematical operators; redundant number systems; signal processing; CORDIC algorithms; FPGA; efficient mapping; fanout; full-custom design; iterative algorithm; redundant arithmetic operators; routing delays; Arithmetic; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Iterative algorithms; Routing; Signal processing algorithms; Vectors; Very large scale integration; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Conference_Location

Lafayette, LA

ISSN

1520-6130

Print_ISBN

0-7803-6488-0

Type

conf

DOI

10.1109/SIPS.2000.886732

Filename

886732