Title :
On the study of logarithmic time parallel adders
Author :
Yeh, Wen-Chang ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This work formulates a set of equations to describe logarithmic time parallel adders. The equations can be used to explain several popular fast adder schemes and derive new adder schemes easily. It is shown that if there is an adder constructed from the conditional-sum rule, then we can always obtain another adder based on the carry-lookahead rule with equivalent topology and structure, and vice versa
Keywords :
adders; network topology; parallel processing; signal processing; adder structure; adder topology; carry-lookahead rule; conditional-sum rule; digital signal-processing applications; equations; fast adders; logarithmic time parallel adders; Adders; Complexity theory; Equations; Multiaccess communication; Performance analysis; Topology;
Conference_Titel :
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-6488-0
DOI :
10.1109/SIPS.2000.886744
