Power consumption and performance comparative study of logarithmic-time CMOS adders

We present a comparative study of two types of high performance adders: the Brent-Kung (1982) and the ELM adder. The evaluation is carried out with the goal of reducing power consumption, while trying to keep the influence on performance to a minimum. A variety of approaches to achieve this, such as delay balancing and pipelining, are studied and their effectiveness is assessed for adders of multiple word lengths. Experiments demonstrate that relative power savings as large as 12%, and performance enhancements as large as 6% are possible. It is also shown that the use of these classic techniques by themselves is not as effective as it was initially thought, since the required overhead consumes more power than it is saved. Then, to obtain some real improvements, some new techniques have to be used