DocumentCode
2671367
Title
CMOS device design-in reliability approach in advanced nodes
Author
Huard, Vincent ; Parthasarathy, CR ; Bravaix, Alain ; Guerin, Chloe ; Pion, Emmanuel
Author_Institution
STMicroelectronics, Crolles, France
fYear
2009
fDate
26-30 April 2009
Firstpage
624
Lastpage
633
Abstract
A general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation.
Keywords
CMOS integrated circuits; hot carriers; semiconductor device reliability; CMOS device design-in reliability approach; HCI ageing effect; NBTI; digital product degradation; hot carrier injection; negative bias temperature instability; parameters extraction; Circuit simulation; Degradation; Hot carrier injection; Human computer interaction; Integrated circuit reliability; Negative bias temperature instability; Niobium compounds; Semiconductor device modeling; Stress; Titanium compounds; AGE function; Design; HCI; ISCAS; NBTI; Reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2009 IEEE International
Conference_Location
Montreal, QC
ISSN
1541-7026
Print_ISBN
978-1-4244-2888-5
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2009.5173321
Filename
5173321
Link To Document