Extended time handling strategies for the improvement of prediction accuracy in event driven power estimation

This paper presents a methodology for calculating very accurate mean power estimates for integrated digital CMOS circuits at gate level. It is shown that by means of improving the time and history handling algorithm of an event driven simulation system can increase the accuracy of predicted power consumption up to 20% compared to a previous, highly efficient method. The outlined approach is capable of handling complex circuits as well as very large sets of input vectors in an efficient way. It is demonstrated that the use of the proposed method, i.e. a specialized event oriented simulation system calibrated with gate specific parameters, results in overall estimation figures which are comparable to transistor level (SPICE) simulation accuracy and in a speed-up of about 10000. This allows both the simulation of very large circuits and the improvement of key design parameters such as yield during manufacturing process optimization, which typically requires repeated estimation runs. Experimental results for a benchmark circuit are detailed which demonstrate significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation methods