DocumentCode
2671453
Title
Low-power signal processing via error-cancellation
Author
Wang, Lei ; Shanbhag, Naresh R.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fYear
2000
fDate
2000
Firstpage
553
Lastpage
562
Abstract
We present an algorithmic noise-tolerance (ANT) technique for designing low-power DSP systems. The proposed technique achieves substantial energy savings via voltage overscaling, whereby the supply voltage is scaled beyond the minimum supply voltage Vdd-crit at which the architecture operates correctly for a given throughput specification. The resulting input-dependent soft errors are corrected via a low-complexity error canceller and hence is referred to as adaptive error-cancellation. The trade-off between energy savings and algorithmic performance is illustrated by employing a reduced-order least mean square (LMS) algorithm to compensate for the design overhead. Simulation results in a 0.35 μm CMOS technology demonstrate that the proposed technique achieves up to 73% energy savings in a multiuser communication scenario over present-day voltage-scaling, with a 3 dB algorithmic performance loss. Moreover, a 40% energy reduction is obtained over conventional DSP systems without algorithmic performance degradation
Keywords
circuit CAD; digital signal processing chips; least mean squares methods; performance evaluation; CMOS technology; adaptive error-cancellation; algorithmic noise-tolerance; error canceller; input-dependent soft errors; low-power DSP; Algorithm design and analysis; CMOS technology; Digital signal processing; Error correction; Least squares approximation; Performance loss; Signal processing; Signal processing algorithms; Throughput; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location
Lafayette, LA
ISSN
1520-6130
Print_ISBN
0-7803-6488-0
Type
conf
DOI
10.1109/SIPS.2000.886753
Filename
886753
Link To Document