DocumentCode :
2671503
Title :
A painless way to reduce power dissipation by over 18% in Booth-encoded carry-save array multipliers for DSP
Author :
Yu, Zhan ; Wasserman, Larry ; Willson, Alan N., Jr.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
fYear :
2000
fDate :
2000
Firstpage :
571
Lastpage :
580
Abstract :
A very simple reorganization of a Booth-encoded carry-save array multiplier is shown to reduce power dissipation in DSP applications. The proposed architecture, a rather straightforward rearrangement of the standard carry-save array, is particularly suitable for applications where one of the multiplier´s input signals has a large dynamic range. We take advantage of the sign-extension zero-encoding property of a Booth encoder to reduce the total switching activity in the adder array, hence lowering the power dissipation. The proposed structure has been synthesized using Synopsys Design Compiler and the layout has been produced using Cadence Silicon Ensemble in a 0.5-μm technology. The layout displays no penalty in circuit and routing area. Experimental results show that over 18% power reduction can be achieved when the proposed multiplier is used in a multiplexed FIR filter
Keywords :
encoding; integrated circuit design; integrated circuit layout; multiplying circuits; Booth-encoded; Cadence Silicon Ensemble; DSP; Synopsys Design Compiler; carry-save array multipliers; layout; multiplexed FIR filter; power dissipation; Adders; Circuit synthesis; Digital signal processing; Displays; Dynamic range; Finite impulse response filter; Power dissipation; Routing; Signal synthesis; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location :
Lafayette, LA
ISSN :
1520-6130
Print_ISBN :
0-7803-6488-0
Type :
conf
DOI :
10.1109/SIPS.2000.886755
Filename :
886755
Link To Document :
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