Fast ASIP synthesis and power estimation for DSP application

This work applies high-level synthesis (HLS) technique to several algorithms and explores its use as a means of analysing power dissipation from the high level of design. We apply a multi-algorithm synthesis technique as designing an application specific instruction set processor (ASIP) from a customised ASIC. This technique synthesises selected time constrained DSP algorithms to define an application, designs the corresponding ASIP core and extracts the specific instruction-set. Although not as effective as a DSP core solution, this technique provides much of the circuit flexibility while maintaining an available trade-off between performance and power dissipation. This technique contains three power estimators to assist algorithm integration with the view to optimising the embedded system: the first one is acting during the application of usual steps of HLS, the second one is triggered after the complete HLS and uses signal property models, the third one is based on the instruction-set of the designed ASIP core. Those techniques have been implemented in our HLS framework called BSS (Breizh Synthesis System, http://archi.enssat.fr/bss)