High performance code generation for VLIW digital signal processors

VLIW (Very Long Instruction Word) architecture has been widely adopted in latest digital signal processor designs to meet the ever increasing need of computing power in, e.g. multimedia applications. In this paper, we present an efficient and retargetable code generation tool for VLIW based DSPs. To make the code generation tool retargetable, we first developed a versatile coding constraint model to faithfully characterize the target machine´s limitations on hardware resource, pipeline execution and other specific instruction usage. Second, since loop executions account for most of the time consumption, the software pipelining technique was employed to overlap the execution of successive iterations. To generate efficient code for real time applications, a simulated evolution (SE) based code generation module was introduced to derive the steady state loop scheduling. Effective heuristics subject to various coding constraints were developed. In addition, to alleviate the scheduling overhead in checking coding/resource constraints repetitively, bit-parallel verification schemes was devised as well. Several test benches on TI TMS320C62/67X DSP have been conducted to verify the effectiveness of our tool and preliminary results show that it can achieve near hand optimized quality code