Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits

A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a series-gating differential-pair circuit (SGDPC) having only one current source. A 4- valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.